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数字电路设计与计算机体系结构RISC-V版，原书配套视频（Digital Design and Computer Architecture）

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2022-05-29 00:59:13

原视频目录：http://pages.hmc.edu/harris/ddca/ddcarv/ddcarv_videos.html DDCA第三版电子书+配套视频+Lab，特点是基于RISC-V讲解，通过该课程能掌握数字电路设计，FPGA，计算机组成的相关内容。所有资料： https://pan.baidu.com/s/1DRhk32-9YdiJSFhIaXMpSw?pwd=ilbu#list/path=%2F 也可参考基于本书开设的课程：ETH252-0028-00L，DDCA，Prof. Onur Mutlu https://www.bilibili.com/video/BV1mP4y1x7At

计算机体系结构

Asph0delus 发消息

Introduction to DDCA: RISC-V Edition

16:36

DDCA Ch1 - Part 0 Introduction to Digital Design

01:53

DDCA Ch1 - Part 1 Managing Complexity

13:41

DDCA Ch1 - Part 2 Unsigned Binary Numbers

07:09

DDCA Ch1 - Part 3 Hexadecimal Numbers

05:20

DDCA Ch1 - Part 4 Bytes, Nibbles & All That Jazz

04:16

DDCA Ch1 - Part 5 Binary Addition

04:17

DDCA Ch1 - Part 6 Signed Binary Numbers

07:24

DDCA Ch1 - Part 7 Extension

02:41

DDCA Ch1 - Part 8 Logic Gates

09:19

DDCA Ch1 - Part 9 Transistors

09:48

DDCA Ch1 - Part 10 Gates FromTransistors

10:52

DDCA Ch1 - Part 11 Power Consumption of Digital Circuits

07:22

DDCA Ch2 - Part 1 Combinational Logic Introduction

01:38

DDCA Ch2 - Part 2 Combinational Circuits

03:45

DDCA Ch2 - Part 3 Boolean Equations

10:15

DDCA Ch2 - Part 4 Boolean Axioms

02:13

DDCA Ch2 - Part 5 Boolean Theorems of One Variable

04:14

DDCA Ch2 - Part 6 Boolean Theorems of Several Variables

07:57

DDCA Ch2 - Part 7 Simplifying Boolean Equations

05:00

DDCA Ch2 - Part 8 From Logic to Gates

08:30

DDCA Ch2 - Part 9 Bubble Pushing

06:15

DDCA Ch2 - Part 10 X's and Z's, Oh My

05:25

DDCA Ch2 - Part 11 Karnaugh Maps (K-Maps)

10:48

DDCA Ch2 - Part 12 K-Maps with Don't Cares

03:35

DDCA Ch2 - Part 13 Multiplexers

06:04

DDCA Ch2 - Part 14 Decoders

02:27

DDCA Ch2 - Part 15 Timing of Combinational Logic

04:43

DDCA Ch3 - Part 1 Intro to Sequential Logic

04:56

DDCA Ch3 - Part 2 Bistable Circuit

04:41

DDCA Ch3 - Part 3 - SR Latch

12:06

DDCA Ch3 - Part 4 D Latch

08:49

DDCA Ch3 - Part 5 D Flip-Flop

12:53

DDCA Ch3 - Part 6 Flop Variations

17:16

DDCA Ch3 - Part 7 Synchronous Sequential Logic

04:18

DDCA Ch3 - Part 8 Finite State Machines (FSMs)

04:37

DDCA Ch3 - Part 9 Moore FSM Example 1

32:01

DDCA Ch3 - Part 10 Moore FSM Example 2

36:38

DDCA Ch3 - Part 11 Mealy FSM Example

17:49

DDCA Ch3 - Part 12 Factored FSMs

04:34

DDCA Ch3 - Part 13 Timing

25:17

DDCA Ch3 - Part 14 ClockSkew

09:49

DDCA Ch3 - Part 15 Metastability

12:01

DDCA Ch3 - Part 16 Synchronizers

02:00

DDCA Ch3 - Part 17 Parallelism

05:16

DDCA Ch4 - Part 1 - SystemVerilog Introduction-sVy31HJj4lA

13:47

DDCA Ch4 - Part 2 Combinational logic in SystemVerilog

03:10

DDCA Ch4 - Part 3 Delays in SystemVerilog simulations

04:56

DDCA Ch4 - Part 4 Sequential Logic in SystemVerilog

08:33

DDCA Ch4 - Part 5 Combinational logic using always blocks

06:45

DDCA Ch4 - Part 6 SystemVerilog Assignments

00:51

DDCA Ch4 - Part 7 FSMs

07:30

DDCA Ch4 - Part 8 Parameterized Modules

02:17

DDCA Ch4 - Part 9 Testbenches

20:48

DDCA Ch5 - Part 1 Digital Building Blocks Introduction

01:14

DDCA Ch5 - Part 2 Adders Introduction

07:49

DDCA Ch5 - Part 3 Ripple Carry Adders

06:43

DDCA Ch5 - Part 4 Carry Lookahead Adders

02:20

DDCA Ch5 - Part 5 Prefix Adders

38:11

DDCA Ch5 - Part 6 Subtractors & Comparators

04:55

DDCA Ch5 - Part 7 ALUs

20:29

DDCA Ch5 - Part 8 Shifters, Multipliers, & Dividers

40:28

DDCA Ch5 - Part 9 Fixed Point Numbers

07:19

DDCA Ch5 - Part 10 Floating Point Numbers

19:21

DDCA Ch5 - Part 11 Floating Point Addition

07:53

DDCA Ch5 - Part 12 Counters & Shift Registers

13:39

DDCA Ch5 - Part 13 Memory Introduction

11:10

DDCA Ch5 - Part 14 RAM

03:10

DDCA Ch5 - Part 15 ROM

08:53

DDCA Ch5 - Part 16 SystemVerilog Memories

07:07

DDCA Ch5 - Part 17 Logic Arrays

17:36

DDCA Ch6 - Part 1 Architecture Introduction

05:11

DDCA Ch6 - Part 1 RISC-V Architecture Introduction

05:47

DDCA Ch6 - Part 2 RISC-V Instructions

02:48

DDCA Ch6 - Part 3 RISC-V Operands

06:08

DDCA Ch6 - Part 4 RISC-V Memory Instructions

05:33

DDCA Ch6 - Part 5 RISC-V Immediates (Constants)

04:40

DDCA Ch6 - Part 6 Logical Instructions

08:18

DDCA Ch6 - Part 7 RISC-V Multiplication & Division Instructions

02:51

DDCA Ch6 - Part 8 Branches

03:25

DDCA Ch6 - Part 9 RISC-V Conditional Statements

14:19

DDCA Ch6 - Part 10 Arrays

10:09

DDCA Ch6 - Part 11 RISC-V Functions

07:49

DDCA Ch6 - Part 12 The Stack

10:42

DDCA Ch6 - Part 13 Recursive Functions

08:03

DDCA Ch6 - Part 14 Jumps & Pseudoinstructions

09:05

DDCA Ch6 - Part 15 RISC-V Machine Instructions R-Type

07:02

DDCA Ch6 - Part 16 More Machine Language Formats

13:51

DDCA Ch6 - Part 17 RISC-V Immediate Encodings

03:50

DDCA Ch6 - Part 18 Decoding Machine Language & Addressing Operands

07:48

DDCA Ch6 - Part 19 Compiling, Assembling, and Loading Programs

12:51

DDCA Ch6 - Part 20 Big-Endian and Little-Endian Memory

02:51

DDCA Ch6 - Part 21 Signed and Unsigned RISC-V Instructions

08:12

DDCA Ch6 - Part 22 RISC-V Compressed Instructions

04:57

DDCA Ch6 - Part 23 RISC-V Floating-Point Instructions

04:58

DDCA Ch7 - Part 1 Microarchitecture Introduction

06:46

DDCA Ch7 - Part 2 RISC-V Single-Cycle Processor Datapath lw

07:25

DDCA Ch7 - Part 3 RISC-V Single-Cycle Processor Datapath Extending Instructions

14:34

DDCA Ch7 - Part 4 RISC-V Single-Cycle Processor Control

15:09

DDCA Ch7 - Part 5 RISC-V Single-Cycle Processor Adding Instructions

09:32

DDCA Ch7 - Part 6 RISC-V Single-Cycle Performance

06:00

DDCA Ch7 - Part 6a RISC-V Processor Test Program & Testbench

08:22

DDCA Ch7 - Part 6b RISC-V Single-Cycle Processor Verilog

13:48

DDCA Ch7 - Part 6c Processor Tie Celebration

00:27

DDCA Ch7 - Part 7 Multicycle Processor Datapath for lw

09:20

DDCA Ch7 - part 8 RISC-V Multicycle Processor - Other Instructions

04:41

DDCA Ch7 - Part 9 RISC-V Multicycle Processor Control lw

10:26

DDCA Ch7 - Part 10 RISC-V Multicycle Processor Control Other Instructions

07:24

DDCA Ch7 - Part 11 Extending the RISC-V Multicycle Processor

05:57

DDCA Ch7 - Part 12 Multicycle Processor Performance

04:47

DDCA Ch7 - Part 13 Pipelined Processor

11:26

DDCA Ch7 - Part 14 Pipelined Processor Data Hazards

14:10

DDCA Ch7 - Part 15 Pipelined Processor Control Hazards

03:57

DDCA Ch7 - Part 16 Pipelined Processor Performance

05:56

DDCA Ch7 - Part 17 Advanced Microarchitecture

09:32

DDCA Ch7 - Part 18 Superscalar & Out of Order Processors

11:02

DDCA Ch7 - Part 19 Multithreading & Multiprocessors

04:52

DDCA Ch9 - Part 1 Embedded Systems Introduction

08:22

DDCA Ch9 - Part 2 RISC-V Microcontrollers

07:42

DDCA Ch9 - Part 3 Memory-Mapped IO

08:19

DDCA Ch9 - Part 4 General-Purpose IO (GPIO)

08:37

DDCA Ch9 - Part 5 RISC-V Device Driver

07:28

DDCA Ch9 - Part 6 Timers

04:09

DDCA Ch9 - Part 7 Morse Code Example

04:06

DDCA Ch9 - Part 8 Interfacing

04:13

DDCA Ch9 - Part 9 SPI

18:11

DDCA Ch9 - Part 10 SPI Accelerometer Example

19:58

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